Hybrid 14nm FinFET-Silicon Photonics Technology for Low-Power Tb/s/mm 2 Optical I/O
authorsRakowski, M; Ban, Y; De Heyn, P; Pantano, N; Snyder, B; Balakrishnan, S; Van Huylenbroeck, S; Bogaerts, L; Demeurisse, C; Inoue, F;
publication2018 IEEE Symposium on VLSI Technology
pages221-222
year2018
First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
authorsVandooren, A; Franco, J; Wu, Z; Parvais, B; Li, W; Witters, L; Walke, A; Peng, L; Deshpande, V; Rassoul, N;
publication2018 IEEE International Electron Devices Meeting (IEDM)
pages7.1. 1-7.1. 4
year2018
Key challenges and opportunities for 3D sequential integration
authorsVandooren, A; Witters, L; Franco, J; Mallik, A; Parvais, B; Wu, Z; Li, W; Rosseel, E; Hikkavyy, A; Peng, L;
publication2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
pages1月4日
year2018
Polymer and Bump Planarization for Fine Pitch Micro-Bump Stacking
authorsInoue, Fumihiro; Derakhshandeh, Jaber; Moeller, Berthold; Gokita, Yohei; Duval, Fabrice; Bex, Pieter; Capuz, Giovanni; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik;
publicationECS Meeting Abstracts
number33
pages1135
year2018