Etch process modules development and integration in 3D-SOC applications
authorsTutunjyan, Nina; Sardo, Stefano; De Vos, Joeri; Van Huylenbroeck, Stefaan; Jourdain, Anne; Peng, Lan; Inoue, Fumihiro; Rassoul, Nouredine; Beyer, Gerald; Beyne, Eric;
publicationMicroelectronic Engineering
volume196
pages38-48
year2018
Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling
authorsVandooren, A; Witters, Liesbeth; Franco, Jacopo; Mallik, Arindam; Parvais, Bertrand; Wu, Z; Walke, Amey; Deshpande, V; Rosseel, E; Hikavyy, Andriy;
publication2018 International Conference on IC Design & Technology (ICICDT)
pages145-148
year2018
Influence of Composition of SiCN Film for Surface Activated Bonding
authorsInoue, Fumihiro; Peng, Lan; Iacovo, Serena; Phommahaxay, Alain; Visker, Jakob; Verdonck, Patrick; Meersschaut, Johan; Dara, Praveen; Sleeckx, Erik; Miller, Andy;
publicationECS Transactions
volume86
number5
pages159
year2018
Extreme thinned-wafer bonding using low temperature curable polyimide for advanced wafer level integrations
authorsBertheau, Julien; Inoue, Fumihiro; Phommahaxay, Alain; Iacovo, Serena; Rassoul, Nouredine; Sleeckx, Erik; Rebibs, Kenneth; Miller, Andy; Beyer, Gerald; Beyne, Eric;
publication2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
pages86-91
year2018
Advances in sicn-sicn bonding with high accuracy wafer-to-wafer (w2w) stacking technology
authorsPeng, L; Kim, SW; Iacovo, S; Inoue, F; Phommahaxay, A; Sleeckx, E; De Vos, J; Miller, A; Beyer, G; Beyne, E;
publication2018 IEEE International Interconnect Technology Conference (IITC)
pages179-181
year2018
3-D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
authorsVandooren, Anne; Franco, Jacopo; Parvais, Bertrand; Wu, Z; Witters, L; Walke, A; Li, Wei; Peng, Lan; Deshpande, Veeresh; Bufler, Fabian M;
publicationIEEE Transactions on Electron Devices
volume65
number11
pages5165-5171
year2018
3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525° C with improved reliability
authorsVandooren, Anne; Franco, Jacopo; Parvais, B; Wu, Z; Witters, L; Walke, A; Li, Wei; Peng, Lan; Desphande, Veeresh; Bufler, Fabian M;
publication2018 IEEE Symposium on VLSI Technology
pages69-70
year2018
Hybrid 14nm FinFET-Silicon Photonics Technology for Low-Power Tb/s/mm 2 Optical I/O
authorsRakowski, M; Ban, Y; De Heyn, P; Pantano, N; Snyder, B; Balakrishnan, S; Van Huylenbroeck, S; Bogaerts, L; Demeurisse, C; Inoue, F;
publication2018 IEEE Symposium on VLSI Technology
pages221-222
year2018
First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
authorsVandooren, A; Franco, J; Wu, Z; Parvais, B; Li, W; Witters, L; Walke, A; Peng, L; Deshpande, V; Rassoul, N;
publication2018 IEEE International Electron Devices Meeting (IEDM)
pages7.1. 1-7.1. 4
year2018
Key challenges and opportunities for 3D sequential integration
authorsVandooren, A; Witters, L; Franco, J; Mallik, A; Parvais, B; Wu, Z; Li, W; Rosseel, E; Hikkavyy, A; Peng, L;
publication2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
pages1月4日
year2018